Category:Computer keys
Category:Computer tests
Category:Keyboard features1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a redundancy circuit for replacing a defective cell with a redundancy cell.
2. Description of the Related Art
Semiconductor memory devices are generally divided into a volatile semiconductor memory device such as a dynamic random access memory (DRAM) and a nonvolatile semiconductor memory device such as a static random access memory (SRAM). A DRAM is a volatile semiconductor memory device which loses data stored therein when power is turned off. On the other hand, an SRAM is a nonvolatile semiconductor memory device which holds data stored therein even when power is turned off.
SRAMs generally include a plurality of memory cells arranged in a matrix form. Each memory cell includes a flip-flop circuit, which stores data. The flip-flop circuit includes two access transistors and two drive transistors. The access transistors transfer data from an SRAM cell to a bit line. The drive transistors transfer data on the bit line to a sense amplifier.
Accordingly, when a data input/output circuit for reading or writing data is located on the SRAM cell, the data may be read or written through a bit line. If the data input/output circuit is located outside the SRAM cell, the data may be read or written through a complementary metal oxide semiconductor (CMOS) circuit. Accordingly, it is possible to use the CMOS circuit as a word line driving circuit for driving the word line.
As is well known in the art, a DRAM has a redundancy circuit for replacing a defective cell with a redundancy cell. If a defective cell is detected in a chip, the DRAM uses the redundancy circuit to replace the defective cell with the redundancy cell. Such a DRAM is disclosed in U.S. Pat. No. 5,696,750 entitled “Redundant Cell Circuit For Semiconductor Memory Device” and U.S. Pat. No. 5,892,792 entitled “Integrated Circuit Chip With Redundant Cell Array Having Parallel Input/Output Lines.”
In addition, if the semiconductor memory device, such as an SRAM, has a defect, the SRAM will be repaired using a redundancy circuit. Such a SRAM is disclosed in U.S. Pat. No. 5 ac619d1d87
Related links:
Comments